These drivers have been under some more rigorous testing in a real world application driving a SSTC GDT. In the high noise environment with little to no shielding the following modification to the external circuitry around these drivers have been made to keep them stable. During operation the fast switching of these drivers creates a lot of noise that even the best capacitors seem to do nothing to clean up. The solution was to introduce some supply line resistance this creates a voltage divider with the capacitors impedance to any noise on the line. Now that there is more of a resistive component the noise can be dissipated in the form of heat due to ohms law and the high DV/DT nature of the noise in question.
Q. Why are the diodes not connect directly to +supply and supply GND?
A. These diodes actually have a small capacitance which can couple high frequency noise onto the bus. By having them commutate current through the 1 ohm resistors it allows time for the 10uF capacitor to react (very small parasitic inductance limits its abillity to pass high frequency noise) the 10uF capacitor is a tantalum. This also gives some place to dissipate the freewheeling current as to not drive up the bus voltage to quickly that the bus capacitors and other loads can react.
Q. Zener diode on bus?
A. During testing it was found that spikes up to 20volts may appear, the Zener helps to clamp down these spikes prolonging the life of the capacitors used to decouple the bus and preventing shoot-through on voltage sensitive devices such as the drivers. It also introduces a very tiny capacitance which has a very low parasitic inductance allowing it to smooth out very high freqency noise.
Please note that the alternative to line resistors is a series resistor on the output of the driver but this has the tendency to slow the output waveform which is undesirable and require greater decoupling capacitance.
Important: do not connect N.I. to VCC as you would normally do in logic IC's for this Inverting configuration. You can see in internal IC layout that the inputs are essentially activated by pull-down current like in TTL chips. The pin has a high noise immunity as it requires some significant current to activate the transistor. If noise is a big issue then increase enclosure shielding, use a large value resistor to pull-up to VCC or pull-up the pin to the input voltage logic level (5V) for example. Generally leaving it floating in this setup is fine and during testing in harsh operating environments the pin has not become accidentally activated.
UC3710 Latch-Up Issue
After purchasing many loads of these MOSFET driver IC's there remained a small problem. They were prone to latch-up while running within the devices safe-operating region. On careful inspection of the datasheet I noticed no internal freewheeling diodes on the output driver stage. Since the drivers loads are reactive some fast recovery free-wheeling diodes were added from the output pin to Vcc and GND. However this did nothing to solve the problem.
At this point I started ordering CMOS versions to replace the batch of Schottky drivers but I became curious as to why such IC's would latch-up at all? If you are familiar with CMOS devices or any MOS device you would know that the fabrication process always leaves a parasitic BJT which is shorted out to create a parasitic diode internal to the MOS devices. This parasitic component has the problem of conducting at times you don't want it to and causing latch-up. But these schottky drivers use BJT's not MOS transistors and do not have this latch-up problem unless they are arranged to form a latch themselves. So how was this driver latching-up?
I took the datasheet schematics and cleaned them up a bit; included extra information so I could see the problem clear in my mind. Below is the device in the TO-220 package with the schematic of internal components and the pin-out.
It appears that the device uses some internal logic gates which are not the same schottky transistor process that the input and output stages are advertised to use. I believe that these gates are MOS type as it is easy to implement both the schottky gate process and CMOS process onto the same die. It is now possible to see just why the device will latch-up. First I would like to point out that these drivers are designed to drive Capacitive loads (e.g. the gate of a MOSFET or IGBT) and not Inductive loads like GDT (Gate Drive Transformers). So it seems in any case where a Inductive load is added to the drivers output stage the internal circuit will latchup. Take note of the internal schottky diode labeled to have a 0.560V forward drop (If 1A).Given the load current freewheels its way through this diode the Output Bias voltage will be influenced which through the TSD (Thermal Shutdown Circuit) can put noise on the output of the OR logic gate. This latch-up does not seem to be destructive to the drivers as I would assume current is limited by the Logic Bias circuit to just over 150mA.